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Course	Diploma in VLSI ( VHDL, Verilog )
Diploma in VLSI brochure - Download Here
Duration	4 months
Timing	Theory - 1 hr/per day, Praticals - 2 hr/per day

Introduction

• This intensive course rapidly trains Embedded programmers to develop applications and programs on Real time Environment.
• Learn concepts and skills essential to programming and software development for RTOS-based applications and embedded products.

Audience

• Electronic background young freshers who want to learn Embedded system.

Prerequisites

• Should have basic knowledge on following areas:
• Basic Knowledge On C Programming and Interested to be master in C Language.

Module - 1

Introduction to VLSI

Need for VLSI Technology - Advantages of VLSI - Integration - Origin of EDA tools - Design Styles - Design flow - Application

Digital Electronics

Digital Electronics - Introduction to Digital Electronics - Digital fundamentals concepts - Boolean Algebra - Number Systems - Binary Arithmetic Codes - Logic Gates - Karnaugh Maps - Arithmetic circuits – Adder - Subtractor - Comparator - Multiplier - Divider - Parity Generator - Parity Checker - Combinational Logic – Encoders - Decoders - Multiplexer - Demultiplexer.

Sequential Logic Circuits

Principles of Sequential Logic Circuits - Basics of Sequential Circuits - Flip flops & Latches Flip flop Conversions - Counters & Registers - Finite State Machines - Verifying Counter Design Using Logic Simulator. Memory Devices - Basic Concepts of PLA - PAL - PLD - RAM - ROM - Real Time Implementation - Basic knowledge of Designing Gates using HDL - Working In Simulation Tool and Synthesis Tool.

VHDL

Introduction to VHDL - Why HDL - Types of HDL - Features of VHDL - Basic Data types – bit - bit vector - std_logic - std_logic_vector - std_ulogic - std_ulogic_vector - Data Objects - Example programs - Design of All Basic Gates - Working in simulation Tools - Test Bench Concepts.

Types of VHDL Modeling

Data Flow - Signal Assignment - Selected Signal Assignment - Conditional Signal Assignment - Structural - Component Declaration - Component - Instantiation - Design of NAND Gate - Half Adder - Full Adder. Behavioral - Process Statements - Sequential Statements – Conditional Statements - Multiway Branching - Loop Statements - WAIT statements - Operators and Data types - Logical - Relational ,Shifter - Addition Addition - Multiplication ,Data types – Scalar - Composite.

FSM

Finite State Machines - FSM types - designing of counters using FSM - Memories - Design of RAM and ROM using VHDL.

Module - 2 Packages Subprograms and packages - Functions - Procedures - User defined packages Declaration ,Package Definition - Advanced Topics - Generic - Generate statement - Assertion - Delay Modeling - Synthesis - Introduction to FPGA & CPLD architecture - How to work in synthesis tools & synthesizing the HDL - codes - Kit Architecture. Verilog HDL Why HDL - Types of HDL - Features of Verilog HDL - Verilog Programming Structures - Basic operator – Logical - Example programs - Design of All Basic Gates - Working in simulation Tools - Test Bench Concepts - Operator - Arithmetic - Relational ,Equality - Bitwise - Reduction - Shift - Conditional - Concatenation - Replication - Data Types & Basic Concepts of verilog HDL - Net Types - Register types - Lexical Conventions - Number Specification - Strings - Identifiers & Keywords - Arrays - Memories - Parameters. Types of Verilog HDL Modeling Data Flow Continuous Assignment - Delays - Structural - Component Instantiation - Primitive Gate Modeling - Gate Delays - Behavioral - Structured Procedure Statements - Procedural Assignments - Sequential Statements – Conditional - Multiway Branching - Loop Statements - Timing Controls - Sequential & Parallel Blocks. Advanced Verilog HDL Modeling Procedural Continuos Assignment - Overriding Parameters - Timescale - System Tasks - Compiler Directives - Tasks & Function - Difference between Task & function - Task & Function Declaration - Task & Function Definitions - Finite State Machine Fsm types - Designing of counters using FSM - Memories - Design of RAM and ROM using Verilog HDL. Advanced Topics - File Handling - UDPs - Logic Synthesis with Verilog HDL Synthesis Tool Synthesis - Introduction to FPGA & CPLD architecture - How to work in synthesis tools & synthesizing the HDL - codes - Hardware Interface - Interfacing concepts - Interfacing Keypad - Interfacing ADC-DAC.